Abstract: The heat flux density of chips has increased greatly with the rapid development of microelectronics technology. The multi-layer thermal resistance generated by chip packaging makes the heat dissipation problem more prominent, so it is extremely important to explore numerical methods that can accurately describe the heat dissipation characteristics of three-dimensional chips. At present, there are multiple technical difficulties in chip-level thermal simulation. To address issues such as large errors in numerical modeling of chip microscale, poor simulation accuracy, as well as the numerous thermal resistance levels of packaged chips that are difficult to simplify. This paper takes multi-chip modules as the research object. Based on the thermal resistance network model of chips with multiple thermal resistance levels, an equivalent thermal resistance calculation method is established, which improves the efficiency and accuracy of numerical calculation for 3D packaged chips. The comparison between simulation results and infrared thermal imaging test results shows that the temperature distribution has high consistency, and the temperature error at the same collected position is within 12%. This further verifies the feasibility of chip-level numerical simulation and provides a theoretical method for thermal optimization of multi-chip modules based on packaging forms.