Abstract: Layout placement is a core step in the physical design flow of integrated circuit (IC), directly determining the area, power consumption, performance, and manufacturability of chips. As semiconductor technology advances into ultra-deep submicron and even advanced nanoscale regimes, the complexity of chips grows exponentially, exposing the physical limits and performance bottlenecks of traditional 2D layout. In recent years, 3D integration technology for IC has overcome the physical limitations of planar scaling through layer-by-layer‌ chip stacking, thereby emerging as a critical approach to sustaining Moore's Law‌. A systematic review of the evolution of IC placement algorithms is presented, the core logic and limitations of classical methods as well as machine learning-driven innovative frameworks are analyzed, and the fundamental principles and engineering applications of 3D IC placement techniques are thoroughly investigated in this paper.